Computer Science Principles V11

Clive W. Humphris

SHIFT REGISTERS: Right Shift Register.    


The simple shift register shown will move the incoming data one place to the right for each clock pulse.

Beginning with the least significant bit. The Q output for a D type will go to the logic state of the D input on the application of a clock pulse. Thereby the next flip-flop taking up the previous Q HIGH or LOW.

Data will eventually be shifted out via Q3.

Table of contents

previous page start next page