Computer Science Principles V11

Clive W. Humphris

MEMORY CELLS: Transistor Switch.  


A bipolar Memory Cell is based on the transistor configured as a switch, where it has two states fully saturated and cut off.

Note, the emitter is the input terminal, where no phase inversion takes place between emitter and collector. The output taking up the same logic state as the input.

Consider the base voltage, when the emitter is at 0V the base emitter junction is forward biased and conducts pulling the base down to 0.6V. By making the emitter 5V the base emitter junction is zero biased, no current flows and so no voltage dropped across Rb.

The same applies to Rc when the transistor is switched OFF, no current, therefore no volts are dropped across Rc. Biasing the transistor ON causes it to conduct heavily, limited only by the value of Rc where the collector voltage falls close to zero due to the voltage dropped across Rc. If the device is connected to a 5V supply rail then the output will conform to TTL logic requirements, i.e. 5V and 0V

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