Clive W. Humphris

**FLIP FLOPS: NAND RS Flip-flop. **

Two cross-coupled NAND gates form the RS flip-flop circuit, driven inputs are labelled Set (S) and Reset (R). As the truth table shows there are four possible input combinations.

The device is in a stable state when S = 1 and R = 0 (set) or when R = 1 and S = 0 (reset). Making both the S and R inputs logic 0 retains the previous state of the Q output with NOT Q taking up the opposite state of Q.

When S = 1 and R = 1, Q and NOT Q will both be forced HIGH. However, if R and S are taken LOW, unpredictable outputs result depending upon which gate switches first. This is known as indeterminate state and a major disadvantage of the simple R-S flip-flop.

By ensuring S and R have opposite logic states the device can be made to flip and retain a defined logic state, which is one bit memory.

- Table of Contents
- Interactive eTextbooks
- Computer Hardware
- Data Structures
- Data Files
- Computer Systems
- Data Handling
- System Development
- Computer Programming
- Binary Numbers
- Binary Arithmetic
- Logic Gates 1
- Logic Gates 2
- Logic Families
- Flop Flops
- Combinational Logic
- Counters
- Counting
- Shift Registers
- Logic Interfacing
- Boolean Algebra
- Micro-Computers
- Data Address Bus
- Memory Addressing
- Arithmetic And Logic Unit
- Microprocessor Timing
- Instructions and Control
- Memory Cells
- Microprocessor Memory
- Addressing Modes
- Instruction Set 1
- Instruction Set 2
- Instruction Set 3